Digital circuit partition sizing for gate-level simulations on heterogeneous platforms

Abstract

The scale of integration in digital circuits has been increasing exponentially, according to Moore’s Law. Traditional design and development techniques require constant improvement to keep up with the growth of circuits, giving rise to the EDA industry. In large projects, 70% of the electronic circuit development effort is spent on correctness verification. One such correctness verification technique is simulation, which is capable of finding errors in the design, but it relies on computational effort. To speed up the total execution time, gate-level digital circuits can be simulated in parallel, achieving speedups of up to 14.4x when simulated on heterogeneous platforms. On these heterogeneous platforms, the execution of the simulation requires large circuits to be partitioned to fit the computational resources of the machine running the simulation. We showed that when partitioned using non-optimal size parameters, the simulation of the circuit can have on average 802% higher execution times, since the execution patterns are divided into two clusters with short and long execution times. Given a heterogeneous simulation platform and a combinational digital circuit at the logic gate level, the best partitioning technique would maximize the number of inputs, outputs, and ports in each